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PCIIDE.TXT
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Document: PCI IDE Controllers for OS/2
Maintainer: Patrick Duffy, duffy@theory.chem.ubc.ca
Revision Dates: 11/3/95, 12/3/95, 5/18/96, 5/26/96, 6/2/96
Archived at: ftp.netcom.com, in directory /pub/ab/abe/
CompuServe (GO BENCHMARK)
Web pages: http://warp.eecs.berkeley.edu/os2/workbench/work.htm
http://www.os2forum.or.at/english/info/os2hardwareinfo/
(note that the first URL may not have up-to-date
versions of the lists)
This document is intended for use by individuals and corporations in a
non-commercial manner. It may be distributed freely within those
limitations. Commercial use of this document in any manner requires
prior written permission of the author.
There seems to be a proliferation of PCI IDE hardware both built in to
PCI motherboards or available as separate cards. Some of it is reported
to work well, and some of it is best left unused. Two of these
controllers, the PC Tech RZ1000 and CMD 640, have been the cause of much
discussion on UseNet, as both have serious flaws which could result in
data corruption. Both are very commonly employed in motherboards of all
types (the PC Tech RZ1000 was used in the Intel Premiere series of
boards and the CMD 640 is still used in many motherboards, such as the
Asus P54SP4). The full story is below. I've therefore created this PCI
IDE list so that people will know if their particular PCI IDE
implementation will work with OS/2. I've tried to keep this information
as accurate as possible, but if you spot any flaws or omissions, please
do not hesitate to let me know. Much of this was received from sources
within IBM. You may see square brackets beside certain chipsets. If
the word "confirmed" appears therein, this means that the bug detailed
in the description to follow along with the subsequent fix have been
confirmed to me by IBM. I've placed a '*' beside the controllers which
seem to work well. The vendor's name and PCI ID appear in HEX/decimal
in brackets beside the controller name. Dates in brackets indicate the
last revision date for the related entry.
NEW THIS WEEK
-------------
I've added contact information for Intel to the "Useful numbers" section
below.
Useful numbers: (12/3/95)
---------------
BusLogic: (408) 492-9090 (Voice)
(408) 654-0760 (tech. support -- 7 A.M. - 5 P.M.
Pacific Time, Mon. - Fri.)
(408) 492-9118 (FAX)
(408) 492-1984 (BBS - N81)
techsup@buslogic.com (E-Mail tech. support)
ftp.buslogic.com (FTP site)
www.buslogic.com (WWW site)
CMD: (800) 426-3832 (sales)
(714) 454-0800 (sales)
(714) 455-1656 (FAX)
DTC: (408) 942-4010 (BBS)
(408) 942-4005 (Faxback)
(408) 942-4081 (sales)
(408) 942-4027 (FAX)
www.datatechnology.com (WWW site)
Intel: (800) 628-8686 (tech. support)
FAXBack:
--------
(800) 525-3019 (US or Canada)
+44 1793-432509 (Europe)
+65 256-5350 (Singapore)
+852 2 530-4116 (Hong Kong)
+886 2 514-0815 (Taiwan)
+822 767-2594 (Korea)
+61 2 975-3922 (Australia)
(503) 264-6835 (World wide)
BBSes:
------
(503) 264-7999 (US or Canada/World wide)
+44 1793-432955 (Europe)
+65 256-4776 (Singapore)
+852 2 530-4116 (Hong Kong)
+886 2 718-6422 (Taiwan)
+822 784-3430 (Korea)
+61 2 975-3066 (Australia)
ftp.intel.com (FTP site)
www.intel.com (WWW site)
PC Tech: (612) 345-4555
Promise: www.promise.com (WWW site)
Tekram: www.tekram.com (WWW site)
Chipsets
--------
1) CMD 640 (CMD Technology Inc.: 1095/4245) (9/4/95)
There are _four_ problems with this particular chip. Here's the
first one:
[confirmed]
Channels (two IDE drives may be attached to each IDE channel) cannot
be operated concurrently because there is a single I/O queue for both
channels. Simultaneous reads to both channels will cause data
corruption. This is not mentioned in the chipset errata.
Here's the second one:
[confirmed]
Their stand-alone PCI board does not have a BIOS and appears to
come-up disabled per the PCI definition. Its really difficult to
tell whether a PCI-IDE controller is operating in 'legacy' mode
since (at least) the CMD chipset does not update the PCI config
space with the legacy base port addresses. Also convincing PCI to
route IRQ 14/15 to a PCI Int is problematic unless the motherboard
BIOS explicitly supports this function.
Here's the third one:
[confirmed]
The CMD chipset also has a documented restriction that it will not
support DWORD config write cycles. Of course the Award BIOS on the
(Vobis) motherboard on which testing was being performed did not
issue byte/word config cycles explicitly and instead implemented all
config read/write services as read/modify/write of DWORD data. The
net result was that the system PCI BIOS could not be used to program
the motherboard chipset!
Here's the fourth one:
[confirmed]
Some systems have the floppy drive changeline connected to the same
line as the 640 chipset. With this setup, data corruption can occur.
The reason is this:
The chip fifo is used not only to contain data, but to contain chip
status as well. As a consequence of this, the following could occur:
Floppy I/O starts.
HD I/O starts.
HD I/O is just about finished when floppy I/O finishes and a request
to start different floppy I/O is made.
At this point, the floppy changeline status is read from the floppy
changeline status register, at location 3f7. If there is data in the
CMD chip waiting to go to the disk at this point, two bytes of it are
_removed_ and replaced with the floppy changeline status. This, of
course, causes data corruption.
One person has reported seeing this bug with an Adaptec 1540 SCSI
controller as well.
IBM have released a software fix for this in the form of a new
IBM1S506.ADD; check for PJ19409.ZIP (from ftp-os2.cdrom.com and
elsewhere) to get it.
2) The Intel Triton PCI chipset (Intel: 8086/32902) (5/18/96)
Any board which uses the Intel Triton PCI chipset will have, via the
Triton chipset, support for EIDE built in to the board. The EIDE is
busmastering, and apparently allows for throughputs of up to 22 MB/s.
There are a proliferation of drivers out there for this chipset, and
success is by no means guaranteed with any of them, at least
according to the messages I get. One report says that disk activity
slows down while comm. activity occurs; this is consistent with the
ISA and ATA data lines being shared. Everything _does_ seem to work
with IBM1S506.ADD, although this will not allow you to use the
busmastering capabilities of the chipset. Adding /SMS and /LBA after
IBM1S506.ADD is reported to help performance somewhat. The Triton
chipset also has an additional "feature" whereby when using the
built-in IDE, both channels cannot be operated independently; both
channels are either on or off, meaning that you either use two
interrupts or none. This allows for faster transfers, though.
3) PC Tech RZ1000 (PC Technology Inc.: 1042/4162) (5/18/96)
There are two bugs in this chip, both of which are by now fixed (the
latest BIOS for the Intel Premiere II board checks the chipset
revision and switches the offending features on or off accordingly).
The first has been known for about a year, and has a fix in fixpack
5. Its story is:
Produces accelerated IRQ. IBM1S506.